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19-0123; Rev. 4; 8/96
KIT ATION EVALU ABLE AVAIL
Low-Power, 8-Channel, Serial 12-Bit ADCs
____________________________Features
o 8-Channel Single-Ended or 4-Channel Differential Inputs o Single +5V or 5V Operation o Low Power: 1.5mA (operating mode) 2A (power-down mode) o Internal Track/Hold, 133kHz Sampling Rate o Internal 4.096V Reference (MAX186) o SPI-, QSPI-, Microwire-, TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 20-Pin DIP, SO, SSOP Packages o Evaluation Kit Available
_______________General Description
The MAX186/MAX188 are 12-bit data-acquisition systems that combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual 5V supplies. The analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface directly connects to SPITM, QSPITM and MicrowireTM devices without external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX186/MAX188 use either the internal clock or an external serial-interface clock to perform successive-approximation A/D conversions. The serial interface can operate beyond 4MHz when the internal clock is used. The MAX186 has an internal 4.096V reference while the MAX188 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim . The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10A at reduced sampling rates. The MAX186/MAX188 are available in 20-pin DIP and SO packages, and in a shrink small-outline package (SSOP), that occupies 30% less area than an 8-pin DIP. For applications that call for a parallel interface, see the MAX180/MAX181 data sheet. For anti-aliasing filters, consult the MAX274/MAX275 data sheet.
MAX186/MAX188
______________Ordering Information
PART MAX186_CPP MAX186_CWP MAX186_CAP MAX186DC/D MAX186_EPP MAX186_EWP MAX186_EAP MAX186_MJP TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 20 Plastic DIP 20 SO 20 SSOP Dice* 20 Plastic DIP 20 SO 20 SSOP 20 CERDIP**
Ordering Information continued on last page. NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. Contact factory for availability of A-grade in SSOP package. * Dice are specified at +25C, DC parameters only. * * Contact factory for availability and processing to MIL-STD-883.
____________________Pin Configuration
TOP VIEW
CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 VSS 9 SHDN 10 20 VDD 19 SCLK 18 CS
________________________Applications
Portable Data Logging Data-Acquisition High-Accuracy Process Control Automatic Testing Robotics Battery-Powered Instruments Medical Instruments
SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor.
MAX186 MAX188
17 DIN 16 SSTRB 15 DOUT 14 DGND 13 AGND 12 REFADJ 11 VREF
DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products
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For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VSS to AGND ............................................................+0.3V to -6V VDD to VSS ..............................................................-0.3V to +12V AGND to DGND.....................................................-0.3V to +0.3V CH0-CH7 to AGND, DGND .............(VSS - 0.3V) to (VDD + 0.3V) CH0-CH7 Total Input Current ..........................................20mA VREF to AGND ...........................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 11.11mW/C above +70C) ...........889mW SO (derate 10.00mW/C above +70C) ........................800mW SSOP (derate 8.00mW/C above +70C) .....................640mW CERDIP (derate 11.11mW/C above +70C) ................889mW Operating Temperature Ranges: MAX186_C/MAX188_C ........................................0C to +70C MAX186_E/MAX188_E......................................-40C to +85C MAX186_M/MAX188_M ..................................-55C to +125C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186-- 4.7F capacitor at VREF pin; MAX188--external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution MAX186A/MAX188A MAX186B/MAX188B Relative Accuracy (Note 2) MAX186C MAX188C MAX186D/MAX188D Differential Nonlinearity DNL No missing codes over temperature MAX186A/MAX188A Offset Error MAX186B/MAX188B MAX186C/MAX188C MAX186D/MAX188D MAX186 (all grades) MAX188A Gain Error (Note 3) External reference 4.096V (MAX188) MAX188B MAX188C MAX188D Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise + Distortion Ratio Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk SINAD THD SFDR 65kHz, VIN = 4.096VP-P (Note 4) 80 -85 70 -80 External reference, 4.096V 0.8 0.1 12 0.5 0.5 1.0 0.75 1.0 1 2.0 3.0 3.0 3.0 3.0 1.5 2.0 2.0 3.0 ppm/C LSB LSB LSB LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode) dB dB dB dB
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Low-Power, 8-Channel, Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186-- 4.7F capacitor at VREF pin; MAX188--external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External compensation, 4.7F External Clock Frequency Range ANALOG INPUT Input Voltage Range, Single-Ended and Differential (Note 9) Multiplexer Leakage Current Input Capacitance VREF Output Voltage Unipolar, VSS = 0V Bipolar, VSS = -5V On/off leakage current, VIN = 5V (Note 6) 4.076 0.01 16 4.096 30 30 30 30 2.5 0 4.7 0.01 0.01 1.5 VDD + 50mV 200 12 VDD 50mV 20 1.5 10 350 mV F F % 4.116 30 MAX186_C MAX186A, MAX186B, MAX186_E MAX186C MAX186_M MAX186D Load Regulation (Note 7) Capacitive Bypass at VREF Capacitive Bypass at REFADJ REFADJ Adjustment Range EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V) Input Voltage Range Input Current Input Resistance Shutdown VREF Input Current Buffer Disable Threshold REFADJ 2.50 V A k A V 0mA to 0.5mA output load Internal compensation External compensation Internal compensation External compensation 50 60 80 ppm/C 0 to VREF VREF/2 1 A pF V mA Internal compensation (Note 6) Used for data transfer only 0.1 0.1 10 t CONV tAZ 10 <50 1.7 2.0 0.4 MHz Internal clock External clock, 2MHz, 12 clocks/conversion 5.5 6 1.5 10 s s ns ps MHz SYMBOL -3dB rolloff CONDITIONS MIN TYP 4.5 800 MAX UNITS MHz kHz
MAX186/MAX188
V
INTERNAL REFERENCE (MAX186 only, reference buffer enabled) TA = +25C
VREF Short-Circuit Current
VREF Tempco
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186-- 4.7F capacitor at VREF pin; MAX188--external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Internal compensation mode External compensation mode MAX186 MAX188 MAX186 MAX188 2.4 0.8 0.15 VIN = 0V or VDD (Note 6) VDD - 0.5 0.5 SHDN = VDD SHDN = 0V SHDN = open SHDN = open -100 -4.0 1.5 2.75 100 VDD -1.5 4.0 1 15 MIN 0 4.7 1.678 1.638 50 5 TYP MAX UNITS
EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Reference-Buffer Gain REFADJ Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current, High SHDN Input Current, Low SHDN Input Mid Voltage SHDN Voltage, Floating SHDN Max Allowed Leakage, Mid Input DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage VDD VSS Operating mode Positive Supply Current IDD Fast power-down Full power-down Negative Supply Current ISS Operating mode and fast power-down Full power-down 5 5% 0 or -5 5% 1.5 30 2 2.5 70 10 50 10 V V mA A A VOL VOH IL COUT ISINK = 5mA ISINK = 16mA ISOURCE = 1mA CS = 5V CS = 5V (Note 6) 4 10 15 0.3 0.4 V V A pF VINH VINL VHYST IIN CIN VINH VINL IINH IINL VIM VFLT F V/V A
V V V A pF V V A A V V nA
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Low-Power, 8-Channel, Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186-- 4.7F capacitor at VREF pin; MAX188--external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Positive Supply Rejection (Note 8) Negative Supply Rejection (Note 8) SYMBOL PSR PSR CONDITIONS VDD = 5V 5%; external reference, 4.096V; full-scale input VSS = -5V 5%; external reference, 4.096V; full-scale input MIN TYP 0.06 0.01 MAX 0.5 0.5 UNITS mV mV
MAX186/MAX188
Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX186 - internal reference, offset nulled; MAX188 - external reference (VREF = +4.096V), offset nulled. Note 4: Ground on-channel; sine wave applied to all off channels. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing. Note 7: External load should not change during conversion for specified accuracy. Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only. Note 9: The common-mode range for the analog inputs is from VSS to VDD.
TIMING CHARACTERISTICS
(VDD = 5V 5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable (Note 6) CS Rise to SSTRB Output Disable (Note 6) SSTRB Rise to SCLK Rise (Note 6) SYMBOL tAZ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK CLOAD = 100pF External clock mode only, CLOAD = 100pF External clock mode only, CLOAD = 100pF Internal clock mode only 0 CLOAD = 100pF CLOAD = 100pF CLOAD = 100pF 100 0 200 200 200 200 200 MAX18_ _C/E MAX18_ _M 20 20 CONDITIONS MIN 1.5 100 0 150 200 100 100 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
__________________________________________Typical Operating Characteristics
POWER-SUPPLY REJECTION vs. TEMPERATURE
0.30 0.25 0.20 PSR (LSBs) 0.15 0.10 0.05 0.00 -0.05 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) VREFADJ (V) VDD = +5V 5% VSS = 0V or -5V 2.455 2.456 OFFSET MATCHING (LSBs)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE
0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 -60 -40 -20
2.454
2.453
2.452
0 20 40 60 80 100 120 140 TEMPERATURE (C)
MAX186/MAX188 FFT PLOT - 133kHz
20 0 ft = 10kHz -20 AMPLITUDE (dB) -40 -60 -80 fs = 133kHz ft = 10kHz fs = 133kHz TA = +25C
-100 -120 -140 0 33.25kHz FREQUENCY 66.5kHz
_____________________________________________________________Pin Description
PIN 1-8 9 NAME CH0-CH7 VSS SHDN Sampling Analog Inputs Negative Supply Voltage. Tie to -5V 5% or AGND Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10A (max) supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier (4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7F capacitor to ground when using external compensation mode. Also functions as an input when used with a precision external reference. FUNCTION
10
11
VREF
6
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Low-Power, 8-Channel, Serial 12-Bit ADCs
________________________________________________Pin Description (continued)
PIN 12 13 14 15 16 17 18 19 20 NAME REFADJ AGND DGND DOUT SSTRB DIN CS SCLK VDD FUNCTION Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. Analog Ground. Also IN- Input for single-ended conversions. Digital Ground Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external mode). Serial Data Input. Data is clocked in at the rising edge of SCLK. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.) Positive Supply Voltage, +5V 5%
MAX186/MAX188
+5V
DOUT
DOUT
3k
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND
18 19 17 10 1 2 3 4 5 6 7 8 13
3k DGND
CLOAD
CLOAD DGND b. High-Z to VOL and VOH to VOL
INPUT SHIFT REGISTER
CONTROL LOGIC
INT CLOCK
a. High-Z to VOH and VOL to VOH
OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN12-BIT SAR ADC OUT REF 20k A 1.65
15 16
DOUT SSTRB
Figure 1. Load Circuits for Enable Time
+5V 3k DOUT DOUT
20 14 9
VDD DGND VSS
3k DGND a VOH to High-Z
CLOAD
CLOAD DGND b VOL to High-Z
REFADJ VREF
12 11
+2.46V REFERENCE (MAX186)
+4.096V
MAX186 MAX188
Figure 2. Load Circuits for Disabled Time
Figure 3. Block Diagram
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
_______________Detailed Description
The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188.
12-BIT CAPACITIVE DAC VREF
INPUT MUX
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND
-
CHOLD + 16pF
COMPARATOR ZERO
CSWITCH TRACK
10k RS HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
Pseudo-Differential Input
The sampling architecture of the ADC's analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH7 and IN- is switched to AGND. In differential mode, IN+ and IN- are selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7. Configure the channels with Table 3 and Table 4. In differential mode, IN- and IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within 0.5LSB (0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1F capacitor from AIN- (the selected analog input, respectively) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V IN+) - (V IN-)] from C HOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
T/H SWITCH
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
Figure 4. Equivalent Input Circuit
single-ended inputs, IN- is connected to AGND, and the converter samples the "+" input. If the converter is set up for differential inputs, IN- connects to the "-" input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by: tAZ = 9 x (RS + RIN) x 16pF, where RIN = 5k, RS = the source impedance of the input signal, and tAZ is never less than 1.5s. Note that source impedances below 5k do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's signal bandwidth.
Input Bandwidth
The ADC's input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Track/Hold
The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
VDD 0.1F DGND AGND VSS SSTRB CS SCLK DIN +5V D1 1N4148 REFADJ VREF C1 4.7F +2.5V +2.5V REFERENCE DOUT SSTRB +5V 2MHz OSCILLATOR CH1 CH2 CH3 CH4 DOUT* +5V
OSCILLOSCOPE
SCLK
0V TO 4.096V ANALOG 0.01F INPUT
CH7
MAX186 MAX188
C2 0.01F
SHDN
N.C.
**
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) **REQUIRED FOR MAX188 ONLY. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
Figure 5. Quick-Look Circuit
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog input to VDD and VSS, allow the channel input pins to swing from VSS - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV, or be lower than VSS by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off-channels over two milliamperes, as excessive current will degrade the conversion accuracy of the on-channel. The full-scale input voltage depends on the voltage at VREF. See Tables 1a and 1b.
Table 1a. Unipolar Full Scale and Zero Scale Reference
Internal Reference (MAX186 only) External Reference at REFADJ at VREF Zero Scale 0V 0V 0V Full Scale +4.096V V REFADJ x A* VREF
* A = 1.678 for the MAX186, 1.638 for the MAX188
Table 1b. Bipolar Full Scale, Zero Scale, and Negative Full Scale Reference
Internal Reference (MAX186 only) External Reference at REFADJ at VREF Negative Full Scale -4.096V/2 -1/2VREFADJ x A* -1/2 VREF Zero Scale 0V 0V 0V Full Scale +4.096V/2 +1/2VREFADJ x A* +1/2 VREF
Quick Look
To evaluate the analog performance of the MAX186/MAX188 quickly, use the circuit of Figure 5. The MAX186/MAX188 require a control byte to be written to DIN before each conversion. Tying DIN to +5V feeds in control bytes of $FF (HEX), which trigger
* A = 1.678 for the MAX186, 1.638 for the MAX188
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result comes out of DOUT. Varying the analog input to CH7 should alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK. The MAX186/MAX188 are fully compatible with Microwire and SPI devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. Microwire and SPI both transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). Example: Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode, call it TB1. TB1 should be of the format: 1XXXXX11 Binary, where the Xs denote the particular channel and conversion-mode selected.
How to Start a Conversion
A conversion is started on the MAX186/MAX188 by clocking a control byte into DIN. Each rising edge on SCLK, with CS low, clocks a bit from DIN into the MAX186/MAX188's internal shift register. After CS falls, the first arriving logic "1" bit defines the MSB of the control byte. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 2 shows the control-byte format. Table 2. Control-Byte Format Bit 7 (MSB) START Bit 7(MSB) 6 5 4 3 Bit 6 SEL2 Name START SEL2 SEL1 SEL0 UNI/BIP Bit 5 SEL1 Description Bit 4 SEL0
Bit 3 UNI/BIP
Bit 2 SGL/DIF
Bit 1 PD1
Bit 0 (LSB) PD0
The first logic "1" bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels are used for the conversion. See Tables 3 and 4.
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referred to AGND. In differential mode, the voltage difference between two channels is measured. See Tables 3 and 4. Selects clock and power-down modes. PD1 PD0 Mode 0 0 Full power-down (IQ = 2A) 0 1 Fast power-down (IQ = 30A) 1 0 Internal clock mode 1 1 External clock mode
2
SGL/DIF
1 0(LSB)
PD1 PD0
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
Table 3. Channel Selection in Single-Ended Mode (SGL/DIFF = 1) SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND - - - - - - - -
Table 4. Channel Selection in Differential Mode (SGL/DIFF = 0) SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 - + - + - + - + CH0 + CH1 - + - + - + - CH2 CH3 CH4 CH5 CH6 CH7
2) Use a general-purpose I/O line on the CPU to pull CS on the MAX186/MAX188 low. 3) Transmit TB1 and simultaneously receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 HEX) and simultaneously receive byte RB2. 5) Transmit a byte of all zeros ($00 HEX) and simultaneously receive byte RB3. 6) Pull CS on the MAX186/MAX188 high.
Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 will contain the result of the conversion padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial clock frequency and the amount of dead time between 8-bit transfers. Make sure that the total conversion time does not exceed 120s, to avoid excessive T/H droop. Digital Output In unipolar input mode, the output is straight binary (see Figure 15). For bipolar inputs, the output is twos-complement (see Figure 16). Data is clocked out at the falling edge of SCLK in MSB-first format.
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Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS tACQ SCLK
1 4 8 12 16 20 24
DIN SSTRB
START SEL2 SEL1 SEL0 UNI/ SCL/ PD1 PD0 BIP DIFF
RB2 RB1
B11 MSB B10
RB3
B0 LSB
DOUT A/D STATE IDLE ACQUISITION 1.5s (CLK = 2MHz)
B9
B8
B7
B6
B5
B4
B3
B2
B1
FILLED WITH ZEROS IDLE
CONVERSION
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
CS
***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 7. Detailed Serial-Interface Timing
Internal and External Clock Modes
The MAX186/MAX188 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX186/MAX188. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7 through 10 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (see Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB will output a logic low. Figure 8 shows the SSTRB timing in external clock mode. The conversion must complete in some minimum time, or else droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the clock period exceeds 10s, or if serial-clock interruptions could cause the conversion interval to exceed 120s.
12
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS tSDV SSTRB *** *** *** *** tSTR
tSSTRB
tSSTRB
SCLK
** * *
****
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
21
22
23
24
DIN
START SEL2 SEL1 SEL0 UNI/ SCL/ PD1 PD0 DIP DIFF
SSTRB tCONV DOUT A/D STATE IDLE CONVERSION 10s MAX 1.5s (CLK = 2MHz) ACQUISITION
B11 MSB B10 B9 B2 B1 B0 LSB
FILLED WITH ZEROS
IDLE
Figure 9. Internal Clock Mode Timing
Internal Clock
In internal clock mode, the MAX186/MAX188 generate their own conversion clock internally. This frees the microprocessor from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the processor's convenience, at any clock rate from zero to typically 10MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB will be low for a maximum of 10s, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out at this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge
will produce the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (see Figure 9). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX186/MAX188 and threestates DOUT, but it does not adversely effect an internal clock-mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 10 shows the SSTRB timing in internal clock mode. In internal clock mode, data can be shifted in and out of the MAX186/MAX188 at clock rates exceeding 4.0MHz, provided that the minimum acquisition time, tAZ, is kept above 1.5s.
13
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS * * *
tCONV tCSH SSTRB * * * tSSTRB SCLK * * * tSCK
tCSS
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Data Framing
The falling edge of CS does not start a conversion on the MAX186/MAX188. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low anytime the converter is idle, e.g. after VCC is applied. OR The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto the DOUT pin. If a falling edge on CS forces a start bit before bit 5 (B5) becomes available, then the current conversion will be terminated and a new one started. Thus, the fastest the MAX186/MAX188 can run is 15 clocks per conversion. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can drive the MAX186/MAX188. Figure 11b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled low, internal power-on reset circuitry will activate the MAX186/MAX188 in internal clock mode, ready to convert with SSTRB = high. After the power supplies have been stabilized, the internal reset time is 100s and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN will be interpreted as a start bit. Until a conversion takes place, DOUT will shift out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, the SHDN pin also selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. Compensated or not, the minimum clock rate is 100kHz due to droop on the sample-and-hold. To select external compensation, float SHDN. See the Typical Operating Circuit, which uses a 4.7F capacitor at VREF. A value of 4.7F or greater ensures stability and allows operation of the converter at the full clock speed of 2MHz. External compensation increases power-up time (see the Choosing Power-Down Mode section, and Table 5). Internal compensation requires no external capacitor at VREF, and is selected by pulling SHDN high. Internal compensation allows for shortest power-up times, but is only available using an external clock and reduces the maximum clock rate to 400kHz.
14
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS 1 SCLK DIN DOUT SSTRB S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2 8 1 8 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS SCLK DIN DOUT S CONTROL BYTE 0 S CONTROL BYTE 1 B11 B10 B9 B8 CONVERSION RESULT 1
*** *** *** ***
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 0
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a low-current shutdown state between conversions. Select full power-down or fast power-down mode via bits 7 and 8 of the DIN control byte with SHDN high or floating (see Tables 2 and 6). Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 7 and 8 of DIN word (see Table 7). Full power-down mode turns off all chip functions that draw quiescent current, reducing IDD and ISS typically to 2A. Fast power-down mode turns off all circuitry except the bandgap reference. With the fast power-down mode, the supply current is 30A. Power-up time can be shortened to 5s in internal compensation mode. In both software shutdown modes, the serial interface remains operational, however, the ADC will not convert. Table 5 illustrates how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, the power-up time is 20ms with a 4.7F compensation capacitor (200ms with a 33F capacitor) when the capacitor is fully discharged. In fast power-down, you can eliminate start-up time by
using low-leakage capacitors that will not discharge more than 1/2LSB while shut down. In shutdown, the capacitor has to supply the current into the reference (1.5A typ) and the transient currents at power-up. Figures 12a and 12b illustrate the various power-down sequences in both external and internal clock modes. Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 6, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC will continue to operate in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results may be clocked out while the MAX186/MAX188 have already entered a software power-down. The first logical 1 on DIN will be interpreted as a start bit, and powers up the MAX186/MAX188. Following the start bit, the data input word or control byte also determines clock and power-down modes. For example, if the DIN word contains PD1 = 1, then the chip will remain powered up. If PD1 = 0, a power-down will resume after one conversion.
______________________________________________________________________________________
15
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN
SXXXXX11 SXXXXX01
INTERNAL
EXTERNAL
EXTERNAL
SETS FAST POWER-DOWN MODE
SETS EXTERNAL CLOCK MODE
SXX XXX1 1
DOUT
DATA VALID (12 DATA BITS)
DATA VALID (12 DATA BITS)
VALID DATA INVALID FULL POWER DOWN POWERED UP
MODE
POWERED UP
FAST POWER-DOWN
POWERED UP
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Table 5. Typical Power-Up Delay Times Reference Buffer ReferenceBuffer Compensation Mode Internal Internal External External 4.7 4.7 VREF Capacitor (F) PowerDown Mode Fast Full Fast Full Fast Full Power-Up Delay (sec) 5 300 See Figure 14c See Figure 14c 2 2 Maximum Sampling Rate (ksps) 26 26 133 133 133 133
Enabled Enabled Enabled Enabled Disabled Disabled
Table 6. Software Shutdown and Clock Mode PD1 1 1 0 0 PD0 1 0 1 0 Device Mode External Clock Mode Internal Clock Mode Fast Power-Down Mode Full Power-Down Mode
Table 7. Hard-Wired Shutdown and Compensation Mode
SHDN
State 1 Floating 0
Device Mode Enabled Enabled
Reference-Buffer Compensation Internal Compensation External Compensation N/A
Full Power-Down
16
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CLOCK MODE INTERNAL CLOCK MODE SETS INTERNAL CLOCK MODE
SXXXXX10 SXXXXX00
SETS FULL POWER-DOWN
S
DIN
DOUT
DATA VALID
DATA VALID
SSTRB MODE
CONVERSION POWERED UP
CONVERSION FULL POWER-DOWN
POWERED UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Hardware Power-Down
The SHDN pin places the converter into the full power-down mode. Unlike with the software shut-down modes, conversion is not completed. It stops coincidentally with SHDN being brought low. There is no power-up delay if an external reference is used and is not shut down. The SHDN pin also selects internal or external reference compensation (see Table 7).
Lowest Power at up to 500 Conversions/Channel/Second
The following examples illustrate two different power-down sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 14a depicts the MAX186 power consumption for one or eight channel conversions utilizing full power-down mode and internal reference compensation. A 0.01F bypass capacitor at REFADJ forms an RC filter with the internal 20k reference resistor with a 0.2ms time constant. To achieve full 12-bit accuracy, 10 time constants or 2ms are required after power-up. Waiting 2ms in FASTPD mode instead of full power-up will reduce the power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 13.
Power-Down Sequencing
The MAX186/MAX188 auto power-down modes can save considerable power when operating at less than maximum sample rates. The following discussion illustrates the various power-down sequences.
COMPLETE CONVERSION SEQUENCE 2ms WAIT DIN (ZEROS) 1 00 FULLPD 2.5V REFADJ 0V 4V VREF 0V tBUFFEN 15s = RC = 20k x CREFADJ 1 01 FASTPD 1 NOPD CH1 11 1 CH7 00 FULLPD (ZEROS) 1 01 FASTPD
Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence
______________________________________________________________________________________ 17
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
MAX186 FULL POWER-DOWN
2ms FASTPD WAIT 400kHz EXTERNAL CLOCK INTERNAL COMPENSATION 100 8 CHANNELS
MAX186-14A
MAX186/MAX188 FAST POWER-DOWN
10,000 AVG. SUPPLY CURRENT (A)
1000 AVG. SUPPLY CURRENT (A)
8 CHANNELS 1000
1 CHANNEL 10
1 CHANNEL 100 2MHz EXTERNAL CLOCK EXTERNAL COMPENSATION 50s WAIT
1 0 50 100 150 200 250 300 350 400 450 500 CONVERSIONS PER CHANNEL PER SECOND
10 0 2k 4k 6k 8k 10k 12k 14k 16k 18k CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX186 Supply Current vs. Sample Rate/Second, FULLPD, 400kHz Clock
Figure 14b. MAX186/MAX188 Supply Current vs. Sample Rate/Second, FASTPD, 2MHz Clock
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with external-reference compensation in fast power-down, with one and eight channels converted. The external 4.7F compensation requires a 50s wait after power-up, accomplished by 75 idle clocks after a dummy conversion. This circuit combines fast multi-channel conversion with lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX186/MAX188 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required.
3.0 2.5 POWER-UP DELAY (ms) 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (sec)
External and Internal References
The MAX186 can be used with an internal or external reference, whereas an external reference is required for the MAX188. Diode D1 shown in the Typical Operating Circuit ensures correct start-up. Any standard signal diode can be used. For both parts, an external reference can either be connected directly at the VREF terminal or at the REFADJ pin. An internal buffer is designed to provide 4.096V at VREF for both the MAX186 and MAX188. The MAX186's internally trimmed 2.46V reference is buffered with a gain of 1.678. The MAX188's buffer is trimmed with a buffer gain of 1.638 to scale an external 2.5V reference at REFADJ to 4.096V at VREF. MAX186 Internal Reference The full-scale range of the MAX186 with internal reference is 4.096V with unipolar inputs, and 2.048V with bipolar inputs. The internal reference voltage is adjustable to 1.5% with the Reference-Adjust Circuit of Figure 17.
18
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
External Reference With both the MAX186 and MAX188, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal buffer amplifier. The REFADJ input impedance is typically 20k for the MAX186 and higher than 100k for the MAX188, where the internal reference is omitted. At VREF, the input impedance is a minimum of 12k for DC currents. During conversion, an external reference at VREF must be able to deliver up to 350A DC load current and have an output impedance of 10 or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7F capacitor.
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
OUTPUT CODE FULL-SCALE TRANSITION
11 . . . 111 11 . . . 110 11 . . . 101
011 . . . 111 011 . . . 110 FS = +4.096 2 1LSB = +4.096 4096
000 . . . 010 000 . . . 001 FS = +4.096V 1LSB = FS 4096 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 FS - 3/2LSB FS 100 . . . 001 100 . . . 000
-FS
0V INPUT VOLTAGE (LSBs)
+FS - 1LSB
INPUT VOLTAGE (LSBs)
Figure 15. MAX186/MAX188 Unipolar Transfer Function, 4.096V = Full Scale
Figure 16. MAX186/MAX188 Bipolar Transfer Function, 4.096V/2 = Full Scale
Using the buffered REFADJ input avoids external buffering of the reference. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD.
+5V
MAX186
510k 100k 12 0.01F REFADJ
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 16 shows the bipolar input/output transfer function. Code transitions occur halfway between successive integer LSB values. Output coding is binary with 1 LSB = 1.00mV (4.096V/4096) for unipolar operation and 1 LSB = 1.00mV ((4.096V/2 -4.096V/2)/4096) for bipolar operation. Figure 17, the MAX186 Reference-Adjust Circuit, shows how to adjust the ADC gain in applications that use the internal reference. The circuit provides 1.5% (65LSBs) of gain adjustment range.
24k
Figure 17. MAX186 Reference-Adjust Circuit
Layout, Grounding, Bypassing
For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 18 shows the recommended system ground connections. A single-point analog ground ("star" ground point) should be established at AGND, separate from the logic ground. All other analog grounds
and DGND should be connected to this ground. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass these supplies to the single-point analog ground with 0.1F and 4.7F bypass capacitors close to the MAX186/MAX188. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a lowpass filter, as shown in Figure 18.
______________________________________________________________________________________
19
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
High-Speed Digital Interfacing with QSPI
The MAX186/MAX188 can interface with QSPI at high throughput rates using the circuit in Figure 19. This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU since QSPI incorporates its own micro-sequencer. Figure 19 depicts the MAX186, but the same circuit could be used with the MAX188 by adding an external reference to VREF and connecting REFADJ to VDD. Figure 20 details the code that sets up QSPI for autonomous operation. In external clock mode, the MAX186/MAX188 perform a single-ended, unipolar conversion on each of their eight analog input channels. Figure 21, QSPI Assembly-Code Timing, shows the timing associated with the assembly code of Figure 20. The first byte clocked into the MAX186/MAX188 is the control byte, which triggers the first conversion on CH0. The last two bytes clocked into the MAX186/MAX188 are all zero and clock out the results of the CH7 conversion.
SUPPLIES +5V -5V GND
R* = 10
VDD
AGND
VSS
DGND
+5V
DGND
MAX186/MAX188
DIGITAL CIRCUITRY
* OPTIONAL
Figure 18. Power-Supply Grounding Connection
+5V 0.1F 1 2 3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 V SS V DD 20 SCLK 19 CS 18 SCK PCS0 4.7F V DDI , V DDE , V DDSYN , V STBY
ANALOG INPUTS
4 5 6 7 8 9
MAX186
DIN 17 MOSI MISO
MC68HC16
SSTRB 16 DOUT 15 DGND 14 AGND 13 REFADJ 12 VREF 11 0.01F 0.1F + 4.7F
10 SHDN
V SSI
VSSE
* CLOCK CONNECTIONS NOT SHOWN
Figure 19. MAX186 QSPI Connection
20
______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
*Title : MAX186.ASM * Description : * This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM * is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software * provided in the Motorola 68HC16 Evaluation Kit. * * Roger J.A. Chen, Applications Engineer * MAXIM Integrated Products * November 20, 1992 * ****************************************************************************************************************************************************** INCLUDE `EQUATES.ASM' ;Equates for common reg addrs INCLUDE `ORG00000.ASM' ;initialize reset vector INCLUDE `ORG00008.ASM' ;initialize interrupt vectors ORG $0200 ;start program after interrupt vectors INCLUDE `INITSYS.ASM' ;set EK=F,XK=0,YK=0,ZK=0 ;set sys clock at 16.78 MHz, COP off INCLUDE `INITRAM.ASM' ;turn on internal SRAM at $10000 ;set stack (SK=1, SP=03FE) MAIN: JSR INITQSPI MAINLOOP: JSR READ186 WAIT: LDAA SPSR ANDA #$80 BEQ WAIT ;wait for QSPI to finish BRA MAINLOOP ENDPROGRAM: INITQSPI: ;This routine sets up the QSPI microsequencer to operate on its own. ;The sequencer will read all eight channels of a MAX186/MAX188 each time ;it is triggered. The A/D converter results will be left in the ;receive data RAM. Each 16 bit receive data RAM location will ;have a leading zero, 12 bits of conversion result and three zeros. ; ;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ;A/D Result 0 MSB LSB 0 0 0 ***** Initialize the QSPI Registers ****** PSHA PSHB LDAA #%01111000 STAA QPDR ;idle state for PCS0-3 = high LDAA #%01111011 STAA QPAR ;assign port D to be QSPI LDAA #%01111110 STAA QDDR ;only MISO is an input LDD #$8008 STD SPCR0 ;master mode,16 bits/transfer, ;CPOL=CPHA=0,1MHz Ser Clock LDD #$0000 STD SPCR1 ;set delay between PCS0 and SCK,
Figure 20. MAX186/MAX188 Assembly-Code Listing
______________________________________________________________________________________ 21
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
;set delay between transfers LDD #$0800 STD SPCR2 ;set ENDQP to $8 for 9 transfers ***** Initialize QSPI Command RAM ***** LDAA #$80 ;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD40 ;store first byte in COMMAND RAM LDAA #$C0 ;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD41 STAA $FD42 STAA $FD43 STAA $FD44 STAA $FD45 STAA $FD46 STAA $FD47 LDAA #$40 ;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD48 ***** Initialize QSPI Transmit RAM ***** LDD LDD LDD LDD LDD LDD LDD LDD LDD PULB PULA RTS READ186: ;This routine triggers the QSPI microsequencer to autonomously ;trigger conversions on all 8 channels of the MAX186. Each ;conversion result is stored in the receive data RAM. PSHA LDAA #$80 ORAA SPCR1 STAA SPCR1 ;just set SPE PULA RTS ***** Interrupts/Exceptions ***** BDM: BGND ;exception vectors point here #$008F STD #$00CF STD #$009F STD #$00DF STD #$00AF STD #$00EF STD #$00BF STD #$00FF STD #$0000 STD $FD30 $FD2E $FD2C $FD2A $FD28 $FD26 $FD24 $FD22 $FD20
Figure 20. MAX186/MAX188 Assembly-Code Listing (continued)
22 ______________________________________________________________________________________
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS ****
****
SCLK
****
SSTRB
****
DIN
Figure 21. QSPI Assembly-Code Timing
TMS320C3x to MAX186 Interface
Figure 22 shows an application circuit to interface the MAX186/MAX188 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 23. Use the following steps to initiate a conversion in the MAX186/MAX188 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR of the TMS320 are tied together with the SCLK input of the MAX186/MAX188. 2) The MAX186/MAX188 CS is driven low by the XF_ I/O port of the TMS320 to enable data to be clocked into DIN of the MAX186/MAX188. 3) An 8-bit word (1XXXXX11) should be written to the MAX186/MAX188 to initiate a conversion and place the device into external clock mode. Refer to Table 2 to select the proper XXXXX bit values for your specific application. 4) The SSTRB output of the MAX186/MAX188 is monitored via the FSR input of the TMS320. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX186/MAX188.
Figure 22. MAX186/MAX188 to TMS320 Serial Interface
XF CLKX CS SCLK
TMS320C3x
CLKR DX DR FSR DIN DOUT SSTRB
MAX186 MAX188
5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX186/MAX188 until the next conversion is initiated.
______________________________________________________________________________________
23
Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186/MAX188
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0 HIGH IMPEDANCE HIGH IMPEDANCE
SSTRB
DOUT
MSB
B10
B1
LSB
Figure 23. TMS320 Serial Interface Timing Diagram
__________Typical Operating Circuit
+5V CH0 0V to 4.096V ANALOG INPUTS CH7 MAX186 VDD DGND AGND VSS CS SCLK VREF C1 4.7F REFADJ C2 0.01F DIN DOUT SSTRB SHDN VSS I/O SCK (SK)* MOSI (SO) MISO (SI) C3 0.1F C4 0.1F VDD
___________________Chip Topography
CH1 CH0 VDD CH2 CH3 DIN SCLK
CS
CPU
CH4
SSTRB 0.151" (3.84 mm) CH5 CH6 DGND CH7 AGND VSS SHDN VREF REFADJ AGND 0.117" (2.97 mm) DOUT
_Ordering Information (continued)
PART MAX188_CPP MAX188_CWP MAX188_CAP MAX188DC/D MAX188_EPP MAX188_EWP MAX188_EAP MAX188_MJP PART MAX186EVKIT-DIP TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C TEMP. RANGE 0C to +70C PIN-PACKAGE 20 Plastic DIP 20 SO 20 SSOP Dice* Plastic DIP 20 SO 20 SSOP 20 CERDIP** BOARD TYPE Through-Hole
MAX186/MAX188
TRANSISTOR COUNT: 2278; SUBSTRATE CONNECTED TO VDD
NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. * Dice are specified at +25C, DC parameters only. * * Contact factory for availability and processing to MIL-STD-883.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
Printed USA is a registered trademark of Maxim Integrated Products.
(c) 1996 Maxim Integrated Products

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